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specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. n0410 sy 20101015-s00002 no.a1865-1/13 LV8827LF overview the LV8827LF is a pwm-type driver ic designed for 3-phase brushless motors. the rotational speed can be controlled by inputting the pwm pulse from the outside, and changing duty. the ic incorporates a latch-type constraint protection circuit. features ? i o max = 1.5a (built-in output tr) ? speed control and synchronous rectification using direct pwm input (supports 3.3v inputs) ? 1-hall fg output ? latch type constraint protection circuit (the latch is released by s/s and f/r.) ? forward/reverse switching circuit, hall bias pin ? power save circuit (power save in stop mode) ? current limiter circuit, low-voltage prot ection circuit, overheat protection circuit ? charge pump circuit, 5v regulator output. ? start/stop circuit (short brake when motor is to be stopped) bi-cmos ic for brushless motor drive pwm driver ic orderin g numbe r : ena1865
LV8827LF no.a1865-2/13 specifications absolute maximum ratings at ta = 25 q c parameter symbol conditions ratings unit v cc max v cc pin 36 v supply voltage v g max v g pin 42 v output current i o max t d 500ms *1 1.5 a pd max1 independent ic 0.2 w allowable power dissipation pd max2 mounted on a circuit board.*2 1.35 w junction temperature tj max 150 q c operating temperature topr -40 to +80 q c storage temperature tstg -55 to +150 q c *1 : tj cannot exceed tj max = 150 q c *2 : specified circuit board : 40mm u 50mm u 0.8mm, glass epoxy (four-layer board) allowable operating range at ta = 25 q c parameter symbol conditions ratings unit supply voltage range v cc 8.0 to 35 v 5v constant voltage output current i reg 0 to -10 ma hb pin output current i hb 0 to -200 p a fg pin applied voltage v fg 0 to 6 v fg pin output current i fg 0 to 10 ma electrical characteristics at ta 25 q c, v cc = 24v ratings parameter symbol conditions min typ max unit supply current 1 i cc 1 3.3 4.0 ma supply current 2 i cc 2 at stop 0.7 0.8 ma output block low-side output on resistance r on (l1) i o = 1.0a 0.47 0.65 : high-side output on resistance r on (h1) i o = -1.0a 0.67 0.9 : low-side output leak current i l (l) 50 p a high-side output leak current i l (h) -50 p a low-side diode forward voltage v d (l1) i d = -1.0a 1.0 1.2 v high-side diode forward voltage v d (h1) i d = 1.0a 1.1 1.3 v 5v constant-voltage output output voltage vreg i o = -5ma 4.8 5.1 5.4 v line regulation ' v (reg1) v cc = 8.0 to 35v, i o = -5ma 50 mv load regulation ' v (reg2) i o = -5m to -10ma 100 mv hall amplifier input bias current ib (ha) -2 p a common-mode input voltage range 1 vicm1 when using hall elements 0.3 vreg-1.7 v common-mode input voltage range 2 vicm2 at one-si de input bias (hall ic application) 0 vreg v hall input sensitivity vhin sin wave 80 mvp-p hysteresis width ' v in (ha) 9 20 35 mv input voltage low o high vslh 3 9 16 mv input voltage high o low vshl -19 -11 -5 mv csd oscillator circuit high level output voltage v oh (csd) 2.7 3.0 3.3 v low level output voltage v ol (csd) 0.9 1.1 1.3 v amplitude v (csd) 1.6 1.9 2.2 vp-p external capacitor charge current ichg1 (csd) vchg1 = 2.0v -14 -11.5 -9 p a external capacitor discharge current ichg2 (csd) vchg2 = 2.0v 9.5 12 14.5 p a oscillation frequency f (csd) c = 0.022 p f (design target value) 130 hz charge pump output (vg pin) output voltage vgout v cc +4.5 v continued on next page.
LV8827LF no.a1865-3/13 continued from preceding page. ratings parameter symbol conditions min typ max unit cp1 pin output on resistance (high level) v oh (cp1) icp1 = -2ma 500 700 : output on resistance (low level) v ol (cp1) icp1 = 2ma 350 500 : charge pump frequency f (cp) 82 103 124 khz internal pwm frequency oscillation frequency f (pwm) 41 51.5 62 khz current limiter operation limiter voltage vrf 0.19 0.21 0.23 v thermal shutdown operation thermal shutdown operation temperature tsd *design target value (junction temperature) 150 165 180 q c hysteresis width ' tsd *design target value (junction temperature) 30 q c hb pin output voltage vhb ihb = -100 p a 3.4 3.6 3.8 v low-voltage protection (5v constant-voltage output detection) operation voltage vsd 3.95 4.15 4.35 v hysteresis width ' vsd 0.2 0.3 0.4 v fg pin (3fg pin) output on resistance vol (fg) ifg = 5ma 40 60 : output leak current il (fg) v o = 5v 10 p a s/s pin high level input voltage v ih (ss) 2.0 vreg v low level input voltage v il (ss) 0 1.0 v input open voltage v io (ss) vreg-2.2 vreg-2.0 vreg-1.8 v hysteresis width v is (ss) 0.25 0.33 0.4 v high level input current i ih (ss) v ss = vreg 45 60 75 p a low level input current i il (ss) v ss = 0v -115 -90 -65 p a pwmin pin recommended input frequency f (pwin) 0.5 60 khz high level input voltage v ih (pwin) 2.0 vreg v low level input voltage v il (pwin) 0 1.0 v input open voltage v io (pwin) vreg-2.2 vreg-2.0 vreg-1.8 v hysteresis width v is (pwin) 0.25 0.33 0.4 v high level input current i ih (pwin) vpwin = vreg 45 60 75 p a low level input current i il (pwin) vpwin = 0v -115 -90 -65 p a f/r pin high level input voltage v ih (fr) *design target value 2.0 vreg v low level input voltage v il (fr) *design target value 0 1.0 v input open voltage v io (fr) vreg-2.2 vreg-2.0 vreg-1.8 v hysteresis width v is (fr) *design target value 0.25 0.33 0.4 v high level input current i ih (fr) vf/r = vreg 45 60 75 p a low level input current i il (fr) vf/r = 0v -115 -90 -65 p a * : design target value and no measurement is made.
LV8827LF no.a1865-4/13 package dimensions unit : mm (typ) 3400 pin assignment pd max ? ta 0 0.756 0.112 1.35 0.2 1 1.5 0.5 2 --40 --20 80 60 20 40 0 100 ambient temperature, ta -- c allowable power dissipation, pd max -- w specified board : 40 1 in3 - 2 in3 + 3 in2 - 4 in2 + 5 in1 - 6 in1 + 18 pgnd 17 rf 16 out2 15 out3 14 out1 13 vg 24 hb 23 pwmin 22 csd 21 f/r 20 fg 19 s/s 7 sgnd 8 vreg 9 cp2 10 cp1 11 v cc 1 12 v cc 2 sanyo : vqfn24k(4.0x4.0) 4.0 4.0 0.85 max 0.0 nom (0.8) top view side view side view bottom view (2.4) (2.4) 0.45 1 24 12 2 (0.75) 0.5 0.25
LV8827LF no.a1865-5/13 three-phase logic truth table (in = ?high? indicates the state where in+ > in-.) ("h" = source, "l" = sink, and "m" = output off are shown with out1 to 3.) f/r = a h ? f/r = a l ? output in1 in2 in3 in1 in2 in3 out1 out2 out3 h l h l h l l h m h l l l h h l m h h h l l l h m l h l h l h l h h l m l h h h l l h m l l l h h h l m h l f/r output in1 in2 in3 fg h l h l h l l l h h l l l h l h l h h h l l h h s/s pin, pwmin pin input state s/s pin pwmin pin high or open stop (short brake) output off low start output on csd function when the s/s pin is in a stop state o protection released and count reset (initial reset) when the f/r pin is switched o protection released and count reset when 0% duty is detected at the pwmin pin input o protection released and count reset when low-voltage condition is detected o protection released and count reset (initial reset) when tsd condition is detected o stop counting
LV8827LF no.a1865-6/13 internal equivalent circuit and sa mple external component circuit csd osc csd control circuit mosc lda 3fg fg hall hys amp fg fg output f/r f/r f/r input pwmin pwmin pwmin input s/s s/s s/s input + hb tsd driver hb in3 - in3 + in2 - in2 + in1 - in1 + v cc pgnd out3 out2 out1 cp2 cp1 vg v cc 2 v cc 1 vreg v cc sgnd rf curr lim lvsd vreg charge pump
LV8827LF no.a1865-7/13 pin functions pin no. pin name pin function equivalent circuit 1 2 3 4 5 6 in3 - in3 + in2 - in2 + in1 - in1 + hall input pin. ? high when in + ! in - . low in reverse relationship. the input amplitude of over 100mvp-p (differential) is desirable in the hall inputs. insert a capacitor between the in + and in - pins if the noise on the hall signal is a problem. vreg 500 5 3 1 500 6 4 2 7 sgnd control circuit block ground pin. 8 vreg 5v regulator output pin (control circuit power supply). insert a capacitor between this pin and ground for stabilization. about 0.1 p f is necessary. v cc 50 8 9 10 cp2 cp1 charge pump capacitor connection pin. insert capacitor between cp1 and cp2. 11 v cc 1 control power pin. insert a capacitor between this pin and ground to prevent the influence of noise, etc. 12 v cc 2 output power pin. insert a capacitor between this pin and ground to prevent the influence of noise, etc. 13 vg charge pump output pin. (upper-side fet gate power supply) insert a capacitor between this pin and v cc . v cc 300 200 cp cg 10 13 9 continued on next page.
LV8827LF no.a1865-8/13 continued from preceding page. pin no. pin name pin function equivalent circuit 14 15 16 out1 out3 out2 output pin. pwm is controlled by the upper-side fet. v cc 14 15 16 17 17 rf output current detection pin. insert a low resistance resistor (rf) between this pin and ground. vreg 5k 17 18 pgnd out circuit block ground pin. 19 s/s pin to select the start/stop type. stop = high or open start = low vreg 5k 50k 75k 19 20 fg fg signal output pin. 1-hall fg (in1). open drain output. 20 vreg continued on next page.
LV8827LF no.a1865-9/13 continued from preceding page. pin no. pin name pin function equivalent circuit 21 f/r pin to select the forward/reverse type. this pin goes to the high level when open. vreg 5k 50k 75k 21 22 csd pin to set the constraint protection circuit operating time and initial reset pulse. insert a capacitor between this pin and ground. insert a resistor in parallel with the capacitor if the protection circuit is not to be used. 500 22 vreg 23 pwmin external pwm input pin. apply an external pwm input signal to this pin. (input frequency range is from 0.5 to 60khz.) pwm on = low pwm off = high or open 23 vreg 5k 50k 75k 24 hb hall bias pin (3.6v output). connect an npn transistor. (see ?5 hall input signal.") vreg 300 250 24
LV8827LF no.a1865-10/13 description of LV8827LF 1. output drive circuit this ic adopts a direct pwm drive method to reduce power loss in the output. it regulates the drive force of the motor by changing the output on duty. the output pwm switching is performed by the upper-side output transistor. the current regeneration route during the normal pwmoff passes through the parasitic diode of the output dmos. this ic performs synchronous rectification, and is intended to reduce heat generation compared to diode regeneration. 2. current limiter circuit the current limiter circuit limits the ou tput current peak value to a leve l determined by the equation i = v rf /rf (v rf = 0.21v (typical), rf: current detection resistor). this circuit suppresses the output current by reducing the output on duty. the current limiter circuit has an operation delay (approx. 7 00ns) to detect reverse recovery current flowing in the diode due to the pwm operation, and prevent a malfunction of the current limiting operation. if the coil resistance of the motor is small, or the inductance is low, the current at st artup (the state in which there is no back electromotive force generated in the motor) will change rapidly. as a result, the operation delay may sometimes cause the current limiting operation to take place at a value above the set current. in such a case, it is necessary to se t the current li mit value while taking into consideration the incr ease in current due to the delay. * regarding the pwm frequency in the current limiter circuit the pwm frequency in the current limiter circuit is dete rmined by the internal reference oscillator, and is approximately 50khz. 3. speed control method pulses are input to the pwmin pin, and the output can be controlled by varying the duty cycle of these pulses. when a low-level input voltage is applied to the pwmin pin, the output at the pwm side (upper side) is set to on. when a high-level input voltage is applied to the pwmin pin, the output at the pwm side (upper side) is set to off. if it is necessary to input pulses using inverted logic, this can be done by adding an external transistor (npn). it is judged duty=0%, count reset and the hb pin output of the csd circuit become "l" when the input of the pwmin pin becomes "h" level during the fixed time, and it enters the state of a short brake. 4. constraint protection circuit the LV8827LF includes a constraint protection circuit for protecting the ic and the motor in a motor constraint mode. this circuit operates when the motor is in an operation condition and the hall signal does not switch over for a certain period. note that while this constraint protection is operating, the upper-side output transistor will be off. time setting is performed according to the capacitance of the capacitor connected to the csd pin. set time (s) | 90 u c ( p f) when a 0.022 p f capacitor is connected, the protectio n time becomes approximately 2.0 seconds. the set time must be selected to a value that provides adequate margin with respect to the motor startup time. conditions for releasing the constraint protection state: ? when the s/s pin is in a stop state o protection released and count reset(initial reset) ? when the f/r pin is switched o protection released and count reset ? when 0% duty is detected at the pwmin pin input o protection released and count reset ? when low-voltage condition is detected o protection released and count reset (initial reset) (? when tsd condition is detected o stop counting) the csd pin also functions as the initial reset pulse generation pin. if it is connected to ground, the logic circuit will go into a reset state, preventing speed control from taking pl ace. consequently, when not using constraint protection, connect a resistor of approximately 220k : and a capacitor of about 4700pf in parallel to ground.
LV8827LF no.a1865-11/13 v cc hb 3v constant-voltage output v cc hb 3v constant-voltage output (1) (2) 5. hall input signal a pulse input with the amplitude in excess of the hyster esis (35mv maximum) is required for the hall inputs. it is desirable that the amplitude of the hall input signal be 100mvp-p or more in consideration of the effect of noise and phase displacement. if disturbances to the output waveform (during phase switc hing) occur due to noise, co nnect a capacitor between the hall input pins to prevent such disturbances. in the constrai nt protection circuit, the hall input is utilized as a judgment signal. although the circuit ignores a cert ain amount of noise, caution is necessary. if all three phases of the hall input sign al go to the same input state (hhh or lll), the outputs are all set to the off state. if the hall ic is used, fixing one side of the inputs (either the + or ? side) at a voltage within the common-mode input voltage range (between 0.3v and vreg-1.7v) allows the other input side to be used as an input over the 0v to vreg range.
LV8827LF no.a1865-12/13 6. power saving circu it (start/stop circuit) to save power when the LV8827LF is in the stop state, mo st of the circuit is stopped, aiming at reducing current consumption. if the hall bias pin is used, the current co nsumption in the power-saving mode will be approximately 700 p a. even in the power-saving mode, a 5v regulator voltage is output. also, in the power-saving mode, the ic is in a short break state. (lower-side shorted) 7. power supply stabilization this ic generates a large output current, and employs a sw itching drive method, so the power supply line level can be disturbed easily. for this reason, it is necessary to connect a capacitor (electrolytic) of sufficient capacitance between the v cc pin and ground to ensure a stable voltage. connect the ground side of the capacitor to the pgnd pin, which is the power ground, as close as possible to the pin. if it is not possible to c onnect a capacitor of sufficiently large capacitance close to the pin, connect a ceramic capacitor of approximately 0.1 p f to the vicinity of the pin. if diodes are inserted in the power s upply line to prevent ic destruction resulting from reverse-connecting the power supply, the power supply lines are even more easily disrupted. and even larger capacitor is required. 8. vreg stabilization to stabilize the vreg voltage, which is the power supply for the control circuit, connect a capacitor of 0.1 p f or larger. connect the ground of this capacitor as close as possible to the control block ground (sgnd pin) of the ic. 9. charge pump circuit the voltage is stepped-up by the charge pump circuit, causing the gate voltage of the upper-side output fet to be generated. the voltage is stepped-up by capacitor cp connected between pins cp1 and cp2, causing charge to accumulate in capacitor cg conn ected between pins vg and v cc . the capacitance of cp and cg must always satisfy the following relationship. cg t 4 u cp charging and discharging of capacitor cp take place based on a frequenc y of 100khz. when the capacitance of capacitor cp is large, the current supply capability of power supply vg will increase. howe ver, if the capacitance is too large, the charging and discharging operations will be in sufficient. the larger the capacitance of capacitor cg, the more stable voltage vg will become. however, if the capac itance is made too large, the period during which voltage vg is generated when the power is switched on will become long, so caution is necessary. the capacitance settings of cp and cg should be the following. cp = 0.01 p f cg = 0.1 p f 10. difference point of LV8827LF and lv8829lf this difference that ic is the more fo llowing compared with lv8829lf exists. LV8827LF lv8829lf when duty=0% of pwm input is detected short brake synchronous rectification off (free run) at the low frequency number of pwm input (about 7.5khz under) like synchronous rectification on synchronous rectification off at low on duty of the pwm input (ex. frequency: 20khz, on duty: 3% under) like synchronous rectification on synchronous rectification off backflow current detecting function non it is. (at detection -> synchronous rectification off) 11. metal part at the rear of the ic the metal part at the rear of the ic (exposed die-pad) constitutes the sub ground of the ic, so connect it to the control ground (sgnd pin) and power ground pin (pgnd) at points close to the ic.
LV8827LF ps no.a1865-13/13 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of november, 2010. specifications and inform ation herein are subject to change without notice.

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